Breaking Through the Memory Wall — Breakthroughs and Future of In-Memory Computing Technology
In recent years, the widespread application of artificial intelligence (AI) technology has profoundly transformed our lives. From the precise short-video recommendations on platforms like Douyin, to the intelligent recognition of complex scenarios by autonomous driving systems, from algorithms optimizing logistics and distribution routes, to intelligent assistants providing real-time multilingual translation — the realization of all these conveniences relies on robust computing power support. However, behind the continuous surge in computing power demand, a hidden bottleneck is gradually emerging: the separation between "storage" and "computing".
Since the Von Neumann architecture laid the foundation for modern computers, the separated design of computing units and storage units has become the mainstream. The two interact through a data bus, similar to two workers with clear divisions of labor: one handles data, while the other stores it. Nevertheless, with the exponential growth of data scale, the limitations of this architecture have become increasingly prominent. Frequent data transfer between storage and computing units not only consumes significant time but also leads to a sharp increase in energy consumption. Statistics show that in high-computing-power scenarios, the energy consumption of data transfer accounts for over 80%, becoming a key bottleneck restricting further improvements in computing power — the so-called "memory wall".
In the AI era, computing power is regarded as the core engine driving technological development, and the "memory wall" is equivalent to a huge obstacle suppressing the engine’s performance. How to break through this limitation and fully unleash the potential of computing power? "In-memory computing (IMC) technology" has emerged as the times require, providing a brand-new path to solve this problem.
Proposed by John von Neumann in 1945, the Von Neumann architecture serves as the foundation for modern computer design. A defining feature of this architecture is that programs and data are stored in the same memory and transmitted to the processor for execution through a single channel (bus). As shown in Figure 1, the processor consists of two main components: the computing unit (responsible for calculations) and the control unit (responsible for reading instructions and directing operations). Although this design is simple and clear, it has obvious shortcomings, known as the "Von Neumann bottleneck": instructions and data must be transmitted in a queue through the same channel, resulting in reduced speed; meanwhile, the computing speed of the processor is far faster than the data transmission speed of the memory, often leading to processor idle time waiting for data and thus lowering efficiency. Nevertheless, this architecture remains the basis of modern computers. Through the integration of cache and pipelining technologies, its computing speed has been greatly improved, paving the way for the development of computers.
Figure 1: Schematic Diagram of the Von Neumann Architecture
However, in today’s AI era, with the exponential growth in computing power demand, the limitations of this traditional architecture have gradually become apparent: data needs to be frequently transferred between storage and computing units, and a large amount of time and energy is wasted on data "moving". This invisible "memory wall" has become a key bottleneck restricting the development of computing power.
The memory wall bottleneck is particularly prominent in high-computing-power tasks. The storage bandwidth required for modern AI computing has reached up to 1 PB/s, yet the speed of mainstream memory is far below this standard. For example, the transmission speed of SRAM is only 10–100 TB/s, and that of DRAM is even lower, at 40 GB–1 TB/s. The gap between the two reaches dozens or even hundreds of times. This speed difference makes it difficult for computing units to fully utilize their performance, significantly dragging down the overall efficiency of the system. In addition, the high energy consumption of data transfer is another important manifestation of the memory wall. In natural language processing tasks, data transfer accounts for 82% of total energy consumption. This bottleneck limits the further improvement of computing power in fields such as AI and big data, leading to high costs and energy consumption, and has become a core issue that modern computing architectures must address.
Figure 2: Energy Consumption Comparison between Computing and Storage
Proposed by computer scientist Gene Amdahl, Amdahl’s Law is used to measure the limit of system performance improvement. It states that the overall speedup of a computing system depends on the proportion of the task that can be parallelized. As shown in Figure 3, S represents the speedup (the multiple by which performance improves with n processors); P is the proportion of the program that can be parallelized; (1-P) is the proportion of the program that must be executed serially; and n is the number of processors used in parallel. Theoretically, the larger P is, the more tasks can be parallelized, and the better the speedup effect. However, when the number of processors (n) increases infinitely, the system speedup will infinitely approach 1/(1-P), meaning that even if the parallel part is greatly optimized, the existence of the serial part will still limit the improvement of overall performance.
Figure 3: Amdahl’s Law
Under the Von Neumann architecture, data transfer is a typical serial task, and its transmission speed is far lower than the computing speed, leading to excessive processor waiting time and becoming a core bottleneck of system performance. Therefore, according to Amdahl’s Law, the key to optimizing system performance lies in reducing or even eliminating the serial data transfer process — that is, breaking the "memory wall". This points out the direction for the optimization of modern computing architectures: the deep integration of storage and computing.
To address the storage bottleneck, in-memory computing technology has emerged. The core idea of in-memory computing is to significantly reduce the need for data transfer through the physical integration of storage and computing. Currently, three main solutions have been proposed:
① Processing Near Memory (PNM): By placing computing units close to storage units, the physical distance is shortened, reducing the time and energy consumption of data transmission. Compared with traditional architectures, PNM improves efficiency, but data transfer still exists, failing to fully solve the problem.
Figure 4: Schematic Diagram of Processing Near Memory
② Processing In Memory (PIM): As shown in Figure 5, simple computing functions (such as adders or multipliers) are embedded inside the memory to perform specific tasks (e.g., matrix operations). PIM goes further in reducing data transfer, but its computing capability is limited and only suitable for specific scenarios.
Figure 5: Schematic Diagram of Processing In Memory
③ Computation In Memory (CIM): As the ultimate form of in-memory computing, CIM achieves the deep integration of computing and storage by directly integrating complex computing capabilities into storage units, as shown in Figure 6. CIM not only completely eliminates data transfer but also significantly improves computing density and energy efficiency. It is suitable for scenarios such as AI inference and edge computing, and is an ideal solution for future high-computing-power demands.
Figure 6: Schematic Diagram of Computation In Memory
The development history of in-memory computing technology can be traced back to the 1960s. In 1969, researchers at the Stanford Research Institute first proposed the concept of in-memory computing, arguing that the deep integration of computing and storage units could significantly reduce the latency and energy consumption caused by data transfer. However, due to limitations in hardware technology at that time, this concept remained at the theoretical level and could not be put into practical application. From the 1980s to the 2000s, in-memory computing technology entered the initial practical stage. The academic community attempted to integrate simple computing capabilities (such as addition and logical operations) into memory such as DRAM, pioneering research directions for PNM and PIM. However, progress was slow due to limited memory performance and high manufacturing costs.
The real driving force for in-memory computing technology to enter the breakthrough stage was the rise of new memory technologies in the early 21st century. In 2008, the invention of resistive random-access memory (ReRAM) became an important turning point for in-memory computing technology. This type of memory can not only store data but also directly execute Boolean logic operations. In 2010, HP Labs successfully used ReRAM to complete hardware experiments on simple operations, verifying the feasibility of the in-memory computing architecture. Since then, new storage technologies such as magnetoresistive random-access memory (MRAM) and phase-change memory (PCM) have been successively introduced into in-memory computing research, gradually advancing the technology from theory to practice. Entering the 2010s, the industry began to try applying in-memory computing technology to practical products. For example, Mythic’s M1108 AI chip based on NOR Flash became an early commercial case. After 2020, in-memory computing technology entered the stage of accelerated commercialization. Especially in scenarios such as AI, big data, and edge computing, chips based on the in-memory computing architecture have gradually become the market mainstream due to their advantages of high energy efficiency and low cost. For instance, domestic enterprises such as Zhicun Technology and Xinyuan Semiconductor have successively launched in-memory computing chips for end-side and edge computing, promoting the widespread application of the technology in practical scenarios.
The development history of in-memory computing technology reflects the leapfrog progress of the technology from theoretical conception to industrial application. Today, with the continuous growth of AI model scale and computing power demand, in-memory computing technology, with its unique architectural advantages, is providing an important solution for breaking the memory wall bottleneck and supporting future computing power needs.
Figure 7: Development History of In-Memory Computing Technology
With its advantages of high cost-effectiveness and ultra-low power consumption, in-memory computing technology is gradually becoming a "killer" solution in the field of AI hardware that cannot be ignored. As shown in Figure 8, taking a chip from Company Z as an example, it can achieve 50 GOPS of computing power at a cost of only $0.8, while the cost of traditional CPUs and GPUs to achieve the same computing power is as high as $20 and $30, respectively. More impressively, by directly integrating computing units into storage units, in-memory computing technology greatly reduces data transfer, resulting in an operating power consumption as low as 5uA–3mA and making hardware design more concise and efficient. This makes it particularly outstanding in end-side devices such as smart headsets and smart speakers, as it can not only improve the AI processing capabilities of the devices but also significantly reduce costs. In addition, in-memory computing technology is rapidly expanding to fields such as edge video processing and cloud AI inference. Relying on its efficient computing architecture, it provides a greener and more efficient solution for high-computing-power scenarios, demonstrating broad market prospects.
Figure 8: Advantages of In-Memory Computing Technology
With its high energy efficiency and flexibility, in-memory computing technology is making its mark in computing scenarios at the end, edge, and cloud levels. As shown in Figure 9, on the end side, devices such as smart headsets and voice assistants can achieve complex voice processing and noise reduction functions with extremely low power consumption by equipping in-memory computing chips. For example, a 2MB in-memory computing chip can provide 100 Gops of computing power while significantly reducing device costs. On the edge side, scenarios that require real-time data processing (such as smart cars and AR glasses) value the high performance and energy efficiency of in-memory computing. For instance, a 128MB chip can achieve 64 Tops of computing power, meeting the real-time perception needs in autonomous driving. On the cloud side, as a key technology for next-generation AI chips, in-memory computing, with its ultra-high computing power (e.g., a 2GB chip achieving 1024 Tops), has demonstrated green and efficient potential in model training and inference tasks in data centers.
Figure 9: Application Scenarios of In-Memory Computing Technology
In-memory computing technology not only breaks through tradition in architectural design but also lays the foundation for the future direction of "brain-inspired computing". Unlike traditional computing architectures, the matrix computing model of in-memory computing technology simulates the connection between neurons and synapses in the brain, enabling it to demonstrate remarkable efficiency in neural network operations. For example, in deep learning tasks, the parallel computing capability of in-memory computing technology can quickly handle multi-layer perception and inference tasks. This brain-like processing method allows it to implement more complex scenarios in smart devices, such as speech recognition, image processing, and real-time environmental analysis. In the future, the combination of brain-inspired computing and in-memory computing technology will empower more smart devices, drive a brand-new evolution from hardware to architecture, and bring AI closer to the essence of "intelligence".
Figure 10: Schematic Diagram of Brain-Inspired Computing
Driven by the rapid growth of high-computing-power demands in fields such as AI and big data, in-memory computing technology is becoming an important driving force for the expansion of the semiconductor market. According to data, by 2025, the market size of small-computing-power in-memory computing chips will reach 12.5 billion yuan, with an even broader long-term market space; by 2030, the market size of small-computing-power chips is expected to exceed 106.9 billion yuan, while the market size of large-computing-power chips will reach 6.7 billion yuan. Together, they will drive the overall market size of in-memory computing chips to 113.6 billion yuan. From the perspective of the end-edge-cloud three-tier structure, the end-side market will see the most significant growth, expanding from 11 billion yuan in 2025 to 99.5 billion yuan in 2030, becoming the largest source of growth.
Figure 11: Market Size Forecast of In-Memory Computing Chips (2025–2030)
As the core foundation of in-memory computing technology, the memory market is also booming. From 2019 to 2025, the global memory market is expected to grow from $105 billion to nearly $200 billion, with both DRAM and NAND memory showing dual-line growth. In particular, driven by demand from smart terminals and data centers, NAND memory will account for a higher market share. The maturity of memory technology not only provides a reliable hardware foundation for in-memory computing technology but also promotes the rapid implementation of in-memory computing chips in low-power, high-efficiency computing scenarios.
Figure 12: Global Memory Market (2019–2025)
From smart terminals to edge computing, and then to cloud AI inference, this technology is providing efficient solutions for computing power demands at different levels. Its core advantage stems from the disruptive innovation in traditional computing architectures — implementing computing functions directly within the memory.
Different from traditional "processing near memory", computation in memory goes further, truly realizing the deep integration of storage and computing. It not only demonstrates a hundred-billion-yuan growth potential in terms of market size but also provides diversified implementation paths at the technical level. Next, this article will comprehensively explore how this technology breaks the memory wall and lays the foundation for future computing power upgrades, focusing on the two major technical routes of analog computation in memory and digital computation in memory, as well as their specific implementations in different types of memory.
Analog computation in memory completes operations in memory arrays by directly utilizing physical laws (Ohm’s Law and Kirchhoff’s Law), featuring high energy efficiency and parallel computing capabilities. Taking the RRAM (resistive random-access memory) computation-in-memory matrix in Figure 13 as an example, the conductivity (Gij) of each memory cell represents weight parameters. The input vector [v1, v2, v3] is converted into voltage signals and applied to the horizontal word lines. This generates a current proportional to the conductivity and input voltage. Through current summation along the vertical bit lines, matrix-vector multiplication is achieved (e.g., I1=∑jG1jVj), completing the weighted sum of data. This method of computing directly using the relationship between current and voltage eliminates the need for data transfer, resulting in extremely high energy efficiency, and is particularly suitable for large-scale matrix operations.
Figure 13: Analog Computation-In-Memory Array Based on RRAM
However, analog computation in memory also faces limitations. For example, computing accuracy is affected by signal nonlinearity and noise, making it difficult to apply in high-accuracy scenarios. Nevertheless, its low power consumption and high parallelism make it shine in power-sensitive scenarios such as IoT sensors and wearable devices, providing an efficient solution for end-side AI applications.
Digital computation in memory achieves the deep integration of storage and computing by integrating logical operation units (such as AND gates and adders) inside the memory array, embedding computing functions into storage units. Figure 14 shows a digital computation-in-memory architecture based on SRAM, with the "digital add tree" as its core. In this architecture, the input vector [IN1, IN2, …, INn] is loaded onto the read word lines (RWL) and multiplied bit-by-bit with the stored weight parameters [W1, W2, …, Wn]. Each memory cell completes the weighting operation through a simple multiplier, and then the results are input into the digital add tree for layer-by-layer summation, ultimately outputting the vector dot product result.
Figure 14: Digital Add Tree for SRAM-Based Digital Computation In Memory
Compared with analog computation in memory, digital computation in memory offers higher computing accuracy and can avoid nonlinear errors and noise interference caused by analog signals. However, its hardware implementation is relatively complex. The addition of logic circuits increases the area and power consumption of memory cells, making it more suitable for scenarios with high accuracy requirements and low sensitivity to power consumption, such as cloud AI inference and scientific computing.
Digital computation in memory by leveraging the precise operations of logic circuits and digital signals, digital computation in memory provides a reliable hardware solution for achieving high-precision matrix operations. This technology holds great significance in advancing the development of in-memory computing integration and breaking through the memory wall bottleneck, laying a technical foundation for future cloud computing and high-performance computing.
After understanding the two major technical routes of analog and digital computation in memory, we cannot help but wonder: how are they implemented in specific memory devices? The physical characteristics of different storage technologies determine their specific application methods and advantages in computation in memory.
In the development of in-memory computing integration technology, NAND Flash, as a key representative of traditional memory, has achieved deep integration of storage and computing through its unique memory cell structure and working principle. As shown in Figure 15, the memory cell of NAND Flash consists of a floating-gate structure, with key components including a control gate, floating gate, insulating dielectric layer, and tunneling oxide layer. By adjusting the voltage, the tunneling effect of electrons between the floating gate and the substrate is altered, thereby changing the threshold voltage of the memory cell. This characteristic is not only used to store "0" and "1" states but can also be extended to multi-level storage for higher-density data storage.
Figure 15: Schematic Diagram of NAND Flash Structure
In the context of in-memory computing integration, NAND Flash utilizes the multi-threshold characteristics of the floating gate to perform simple data operations through precise voltage control. For example, when reading data, changes in the current of memory cells can be detected to complete operations such as weighted summation. This physics-based computing method not only reduces the energy consumption of data transfer but also improves the efficiency of large-scale parallel computing.
However, NAND Flash also faces challenges in reliability and lifespan during the implementation of in-memory computing. For instance, the thinning of the tunneling oxide layer may lead to electron leakage and reduced data stability. Through the stacking and optimization of 3D NAND technology, its storage density and performance have been further improved, providing an efficient solution for fields such as smart terminals and edge computing. The structure and working principle of NAND Flash are typical representatives of in-memory computing implementation in traditional memory and also serve as an important cornerstone for future in-memory computing integration technology.
Resistive Random-Access Memory (ReRAM) is a non-volatile storage technology based on resistance changes, which realizes data storage by altering the resistance state of quantum thin-film materials. As shown in Figure 16, its basic structure adopts a metal-insulator-metal (MIM) sandwich design, consisting of a top electrode, resistive layer, and bottom electrode. Among these, the resistive layer is the key component: by applying a voltage, conductive paths (conductive filaments) are formed or broken, switching between a high-resistance state (HRS) and low-resistance state (LRS), which correspond to logic "0" and "1" respectively.
Figure 16: Schematic Diagram of ReRAM Structure
In in-memory computing integration, ReRAM directly completes simple logic operations and weighted summation using its high and low resistance states, without the need for additional computing units. Its simple structure, low energy consumption, and fast read-write speed make it highly suitable for high-density storage and edge computing scenarios. However, ReRAM still faces challenges in the stability of conductive filaments and manufacturing consistency, requiring further optimization for large-scale applications. As a representative of emerging memory, ReRAM provides a new path for technological breakthroughs in in-memory computing integration.
Magnetic Random-Access Memory (MRAM) is a non-volatile storage technology based on Magnetic Tunnel Junctions (MTJ), which achieves data storage through changes in magnetization direction. As shown in Figure 17, its structure consists of a pinned layer, free layer, and tunnel layer. The magnetization direction of the pinned layer remains unchanged, while that of the free layer can be flipped under the action of an external current or electric field. The tunnel layer, located between the two layers, transmits current through the quantum tunneling effect.
Figure 17: Schematic Diagram of MRAM Structure
The working principle of MRAM relies on the relative magnetization directions of the free layer and pinned layer to determine resistance: when the magnetization directions of the two layers are parallel, the resistance is low (low-resistance state, representing "0"); when the directions are antiparallel, the resistance is high (high-resistance state, representing "1"). This characteristic endows MRAM with non-volatility, high read-write speed, and unlimited erasure durability, making it one of the potential hardware implementations for in-memory computing integration technology.
Phase-Change Memory (PCM) utilizes the phase-change properties of materials to achieve data storage by altering the physical state of a storage medium (e.g., germanium-antimony-tellurium alloy, GST). As shown in Figure 18, its core structure includes a top electrode, bottom electrode, heating resistor layer, and phase-change material layer. The phase-change material can switch between a crystalline state (low resistance) and amorphous state (high resistance), corresponding to logic "1" and "0" respectively.
Figure 18: Schematic Diagram of PCM Structure
The working principle of PCM is based on thermal control: the temperature is adjusted via the heating resistor. Rapid cooling keeps the material in an amorphous state (high resistance), while slow cooling allows it to crystallize into a crystalline state (low resistance). This characteristic not only enables data storage but also supports direct simple logic operations, providing hardware support for in-memory computing integration. PCM offers advantages such as non-volatility, high speed, and high storage density; however, due to high power consumption during the writing process, it is currently mainly used in high-performance storage and embedded devices.
The implementation path of in-memory computing integration technology includes both breakthroughs in traditional memory and innovations in emerging memory. From NAND Flash to ReRAM, MRAM, and PCM, each storage technology demonstrates unique advantages.
Among traditional memory technologies, NAND Flash, with its mature technology and high storage density, has achieved initial integration of storage and computing through floating-gate technology. This not only addresses efficiency issues in large-scale data processing but also lays the foundation for in-memory computing integration technology. However, with the diversification of demands and technical bottlenecks, the limitations of NAND Flash have become increasingly apparent.
The emergence of emerging memory has injected new vitality into in-memory computing integration technology. ReRAM realizes the dual functions of simple logic operations and data storage through switching between high and low resistance; MRAM provides a solution for fast read-write and high durability via magnetic tunnel junctions; and PCM excels in both data storage and logic computing by leveraging material phase-change properties. These technologies not only enable the implementation of in-memory computing integration independently but also further expand technical boundaries in terms of storage density, speed, and power consumption.
In summary, both traditional and emerging memory technologies have jointly promoted the development of in-memory computing integration technology, breaking the constraints of the "memory wall" in traditional computing architectures. In the future, these technologies will be further integrated to deliver more efficient and intelligent computing and storage solutions. In-memory computing integration is not only a technological revolution but also an evolutionary path that empowers the future.
In the race for in-memory computing integration technology, the global industrial landscape is evolving rapidly, presenting a dual-track trend of "domestic rise and overseas leadership". Overseas technology giants still hold advantages in the market with their mature technical accumulation and comprehensive industrial chains; meanwhile, domestic enterprises are striving to catch up through technological breakthroughs and capital support, achieving a leap from following to leading in some fields.
In the overseas market, giants such as Samsung and SK Hynix still occupy core positions in traditional storage technologies like NAND Flash and ReRAM. Their robust IDM (Integrated Device Manufacturing) and Fab (Foundry Manufacturing) models provide a solid foundation for efficient storage and computing integration. At the same time, emerging enterprises such as Crossbar and Mythic focus on cutting-edge fields like ReRAM and MRAM, promoting the application of in-memory computing integration technology in high-performance computing and edge devices.
Notably, overseas enterprises not only possess in-depth technical capabilities but also demonstrate strong strength in industrial chain integration and commercial implementation. Samsung has repeatedly set new records in NAND Flash stacking technology, becoming a global benchmark for improving storage density; enterprises like IBM are actively deploying MRAM technology to meet future artificial intelligence computing needs.
In the localization process of in-memory computing integration technology, traditional giants and emerging forces have jointly driven the rapid development of the domestic storage industry. As a world-leading chip foundry, TSMC provides strong manufacturing support for domestic storage technology with its profound accumulation in Flash and SRAM processes. TSMC’s advanced process technology not only helps domestic memory products gain a foothold in the global market but also lays a solid foundation for domestic enterprises to transition from R&D to mass production. In terms of 3D NAND Flash and high-performance SRAM processes, TSMC’s technological leadership remains an important support for domestic enterprises to catch up with international giants.
Meanwhile, the rise of emerging enterprises has injected new vitality into the domestic industry. Shanghai Xinyuan Semiconductor focuses on ReRAM technology R&D and is the first enterprise in mainland China to achieve mass production of ReRAM with advanced processes. The smooth commissioning of its self-built 12-inch pilot production line marks a major breakthrough in China’s emerging memory technology field. Xinyuan’s ReRAM products not only cover terminal and edge computing scenarios but also demonstrate potential in the AI chip field, reflecting the high integration of technological breakthroughs and commercial implementation. In parallel, Hangzhou Zhicun Technology focuses on innovative applications of Flash memory. By launching the WTM series of in-memory computing chips, it has established a presence in multi-scenario applications (end, edge, and cloud) and begun deploying emerging storage technologies such as MRAM, opening up more possibilities for future high-performance storage.
The rise of the domestic storage industry is the result of coordinated progress between traditional giants and emerging forces. In particular, the rapid breakthroughs of Shanghai Xinyuan and Hangzhou Zhicun have provided additional advantages for domestic memory products in global competition within niche markets. Driven by both tradition and innovation, domestic in-memory computing integration technology is launching a strong challenge to the international market with diversified breakthroughs.
Figure 19: Domestic and Overseas Competitive Landscape of In-Memory Computing Integration Technology
In recent years, domestic startups in the in-memory computing integration field have emerged like mushrooms after rain, demonstrating strong momentum in technological innovation and market layout. From traditional Flash to emerging ReRAM and MRAM, various storage technologies have flourished, covering a wide range of application scenarios from terminals to edge and cloud.
Zhicun Technology relies on Flash technology to implement product deployment across end, edge, and cloud scenarios, with a valuation exceeding 2.9 billion yuan.
Xinyuan Semiconductor focuses on ReRAM technology, taking the lead in achieving mass production with 28nm processes and a product yield rate of up to 85%, with a current valuation of over 3 billion yuan.
Houmo Intelligence has pioneered a new path by combining SRAM and ReRAM; the mass production of its H30 chip marks a new stage in domestic in-memory computing integration technology.
The in-depth cultivation of these enterprises in niche fields not only demonstrates the vitality of technological innovation but also highlights diverse investment potential.
From the perspective of capital market performance, in-memory computing integration technology has become a new investment hotspot. The high valuations and financing enthusiasm of these startups indicate that the market has high expectations for the future development of in-memory computing integration technology. The success of enterprises such as Zhicun Technology and Xinyuan Semiconductor not only verifies the market value of emerging storage technologies but also provides capital with an investment path focusing on high-tech fields. For investors, the in-memory computing integration field is at the intersection of technological breakthroughs and large-scale application—seizing opportunities in this field will be a crucial step in deploying future technology industries.
Figure 20: Overview of Domestic Investment Opportunities in In-Memory Computing Integration
The global race for in-memory computing integration technology has entered a fever pitch. Overseas giants maintain their leadership with technical accumulation and industrial chain advantages, while domestic enterprises are narrowing the gap through innovative breakthroughs and capital support. In this technological race, regional development has gradually become a key driving force—from scientific research breakthroughs to industrial clusters, regions across China are leveraging their advantages in technology, talent, and policies to build unique storage ecosystems. The following section will focus on city-level investment opportunities behind regional development and explore how they inject strong impetus into the industrial implementation of in-memory computing integration technology.
In recent years, domestic universities have delivered outstanding performances in scientific research in the in-memory computing integration field. As shown in Figure 21, from Tsinghua University’s memristor-based in-memory computing chips, to the SRAM in-memory computing solution proposed by the Chinese Academy of Sciences, and Nanjing University’s high-energy-efficiency memory technology—universities across China are constantly pushing the technological boundaries of this field. These research efforts are not limited to the theoretical stage but have gradually demonstrated potential for transition from laboratory to practical application.
More notably, significant business opportunities lie behind these technologies. For example, breakthrough progress in memristor-based in-memory computing solutions provides a new path for AI chip optimization; the development of high-energy-efficiency memory lays a technical foundation for edge computing and low-power devices. The research achievements of these universities not only point out the direction of technological development but also bring potential investment opportunities to the market. In-memory computing integration technology is poised to become the next industrial trend.
Figure 21: Overview of Domestic Scientific Research Progress in In-Memory Computing Integration
In recent years, the regional development of in-memory computing integration technology has accelerated, with cities such as Beijing, Shanghai, Hangzhou, Nanjing, and Hefei gradually emerging as important hubs for the storage industry. Relying on the scientific research capabilities of top universities and the technology implementation capabilities of local enterprises, these regions are advancing in parallel in storage technology innovation and application.
Beijing takes Tsinghua University and Peking University as its scientific research core, continuously outputting cutting-edge achievements and converting them into industrial advantages.
Hangzhou’s Zhicun Technology and Hefei’s Ruike Micro have delivered outstanding performances in the Flash and ReRAM fields, opening up new paths for the practical application of in-memory computing integration technology.
Nanjing’s Houmo Intelligence and Shanghai’s Xinyuan Semiconductor focus on SRAM and ReRAM technologies, promoting the implementation of edge computing and AI scenarios through technological breakthroughs.
These cities are not only hotbeds of technological innovation but also inject sustained momentum into the large-scale development of the future storage industry. The integration of scientific research and industry is accelerating the integration of industry, academia, and research, creating unprecedented opportunities for the rise of China’s storage technology.
It is evident that cities across China are promoting the transition of in-memory computing integration technology from laboratory to market through the integration of scientific research resources, technological innovation, and industrial policy support. From end-side to cloud, and from university laboratories to industrial clusters, regional development has become a key engine for breakthroughs in this technology. In the future, with the acceleration of inter-regional collaborative innovation, China is expected to occupy a more important position in the global competition for in-memory computing integration technology, injecting new impetus into the revolutionary development of computing architectures.
The rapid development of regional innovation has created fertile ground for the implementation of in-memory computing integration technology, and these technological breakthroughs have also brought unprecedented opportunities for investors. From scientific research to industrialization, the in-memory computing integration field is entering a critical period of value release. This section will analyze the potential and direction of this field from the perspective of investment logic, providing insights for deploying future technology industries.
As a brand-new computing architecture in the post-Moore era, in-memory computing integration technology is subverting the traditional separated model of storage and computing, and its transformative significance is comparable to a technological revolution. As Moore’s Law gradually approaches its limits, the improvement of computing capabilities of traditional chips has begun to slow down. In contrast, in-memory computing integration technology has become an inevitable choice for future computing development by breaking through the "memory wall" bottleneck. Especially in fields requiring high-efficiency computing power (such as artificial intelligence and big data), this technology can significantly improve efficiency and reduce costs by integrating computing capabilities into storage units, demonstrating great market appeal.
From the perspective of market potential, in-memory computing integration technology has broad application scenarios, covering end-side devices, edge computing, and cloud computing. It is expected that the relevant market size will reach the hundred-billion-yuan level by 2030. This growth potential not only reflects its revolutionary role in driving the technology industry but also provides long-term value assurance for investors. Additionally, China’s relatively narrow gap with international standards in this technological field enhances the possibility of "overtaking on curves", making it a key breakthrough for achieving technological independence and self-reliance. It can be said that in-memory computing integration technology carries the hope of future industrial upgrading and serves as a core pillar of investment logic.
Currently, in-memory computing integration technology is in the early stage of industrialization, and the maturity of technology and processes still requires time—but this is precisely the investment window. Domestic enterprises have demonstrated strong R&D potential and flexible market responsiveness in this field, and have initially shown core competitiveness in key links such as manufacturing processes and algorithm optimization. Selecting enterprises capable of improving process levels and overcoming manufacturing bottlenecks will be the key to identifying future unicorn enterprises.
Furthermore, the value of in-memory computing integration technology is also reflected in its ability to meet the needs of multi-level markets such as end devices, edge computing, and cloud computing, with broad application potential ranging from the consumer end to data centers. Particularly in the end-device and edge computing markets, some enterprises with cutting-edge technological reserves have already started small-batch production and achieved customer onboarding. Such enterprises can not only drive short-term performance growth but also achieve explosive development in the next few years, creating excess returns for investors. For investors pursuing a balance between innovation and returns, in-memory computing integration is undoubtedly a field worthy of long-term layout.
From the glories and limitations of the Von Neumann architecture to the emergence of in-memory computing integration technology, we are at the forefront of the transformation of computing architectures. In-memory computing integration technology not only breaks through the "memory wall"—a long-standing bottleneck restricting the development of computing power—but also injects new momentum into fields such as artificial intelligence and big data. From smart headsets to autonomous driving, and from edge computing to cloud inference, this technology is quietly changing our daily lives.
Globally, major technology giants and startups are engaged in fierce competition in in-memory computing integration technology. Meanwhile, China's domestic industry is gradually narrowing the gap through technological breakthroughs and regional collaboration, and even achieving surpassing in some niche areas. The in-depth integration of scientific research capabilities, capital support, and industrialization implementation provides a solid foundation for China to gain more initiative in this field.
In the future, in-memory computing integration technology will not only be a core driver of scientific and technological innovation but also is likely to become a crucial engine for the development of the intelligent era. Whether it is the expansion of the hundred-billion-yuan-level market or the comprehensive upgrading of the industrial chain, in-memory computing integration will write a new chapter in computing architectures. We stand at the crossroads of history, witnessing the leap of technology and embracing brand-new development opportunities. In this journey toward a smart future, in-memory computing integration technology is opening the door to infinite possibilities for us.
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Source: Xu Xiwen, Investment Department V
Review: Xue Yao
Release: You Yi
